TILE64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose...
5 KB (396 words) - 20:38, 3 February 2024
MIPS, MN103, OpenRISC, PA-RISC, PowerPC, s390, S+core, SuperH, SPARC, TILE64, Unicore32, x86, Xtensa, RISC-V (with Linux-libre kernel only) Kernel type...
34 KB (3,109 words) - 23:30, 17 September 2024
embedded processor design. The company shipped multiple processors in the TILE64, TILEPro64, and TILE-Gx lines. After a series of company acquisitions, Tilera's...
10 KB (859 words) - 06:51, 24 August 2024
Fujitsu SPARC64 VI; IBM POWER6, PowerPC BGP; Sun UltraSPARC T2; Tilera TILE64 2008 AMD Opteron Shanghai, Phenom; Fujitsu SPARC64 VII; IBM PowerXCell 8i...
53 KB (4,935 words) - 19:14, 23 September 2024
multimedia video processor. TMS320TMS320C66, 2-, 4-, 8-core DSP. Tilera TILE64, a 64-core 32-bit processor. TILE-Gx, a 72-core 64-bit processor. XMOS Software...
51 KB (5,715 words) - 23:04, 7 September 2024
Thule All pages with titles beginning with Tile Tiler (Masonic) Tilera TILE64 a 64-way multi-core central processor unit Tiling (disambiguation) Tessellation...
2 KB (210 words) - 13:43, 20 December 2021
4 GHz 90 nm 543 2 / 1 2007 UltraSPARC T2 Sun 1–1.4 GHz 65 nm 503 8 / 1 2007 TILE64 Tilera 600–900 MHz 90–45 nm ? 64 / 1 2007 Opteron "Barcelona" AMD 1.8–3...
52 KB (2,639 words) - 08:29, 8 September 2024
included in Open64. The very advanced compiler from Tilera, for its 64-core TILE64 chip, is based on Blackbird. Open64 exists in many forks, each of which...
8 KB (674 words) - 20:57, 16 September 2024
random number generator, RSA accelerator. Fabrication process: TSMC 40nm. TILE64 TILEPro64 "Tilera Corporation Joins China's Wireless TD Forum as a Senior...
8 KB (372 words) - 02:29, 26 April 2024
equipped with computing accelerators such as NVidia GPGPUs, Xeon Phi, Tilera TILE64. The main design philosophy of FastFlow is to provide application designers...
68 KB (8,819 words) - 21:55, 19 December 2023
family incorporates a number of enhancements over Tilera's first generation TILE64 family: "Distributed Dynamic Cache" (DDC) system that uses a separate mesh...
6 KB (555 words) - 14:56, 10 September 2024