• x87 is a floating-point-related subset of the x86 architecture instruction set. It originated as an extension of the 8086 instruction set in the form...
    24 KB (2,517 words) - 21:16, 11 December 2024
  • instructions provided by x87 obey PC and RC. x87 coprocessors (other than the 8087) handle exceptions in a fairly unusual way. When an x87 instruction generates...
    255 KB (14,178 words) - 21:48, 15 December 2024
  • mode switching penalty for issuing x87 instructions present in MMX because it is sharing register space with the x87 FPU. The SSE2 also complements the...
    9 KB (1,236 words) - 08:21, 14 August 2024
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    independent clocking schemes. CORDIC routines have been implemented in Intel x87 coprocessors (8087, 80287, 80387) up to the 80486 microprocessor series,...
    16 KB (1,654 words) - 09:49, 2 November 2024
  • do have limited support for the decimal numeral system. In addition, the x87 part supports a unique 18-digit (ten-byte) BCD format that can be loaded...
    10 KB (1,363 words) - 07:53, 15 January 2024
  • aliases for the existing x87 floating-point unit (FPU) registers, which context switches would already save and restore. Unlike the x87 registers, which behave...
    15 KB (1,447 words) - 05:20, 31 August 2024
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    integrated this x87 functionality on chip which made the x87 instructions a de facto integral part of the x86 instruction set. Each x87 register, known...
    105 KB (10,747 words) - 10:04, 20 December 2024
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    The available speed version were 4.77 (5), 8, and 10 MHz. There were later x87 coprocessors for the 80186, 80286, 80386, and 80386SX processors. Starting...
    25 KB (2,898 words) - 23:16, 6 August 2024
  • the standard x87 FPU, 3DNow! instructions and x87 instructions cannot be executed simultaneously. However, because it is aliased to the x87 FPU, the 3DNow...
    16 KB (1,741 words) - 23:50, 4 September 2024
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    supported through mandatory SSE2 instructions in 64-bit mode. While the older x87 FPU and MMX registers are still available, they are generally superceded...
    117 KB (11,630 words) - 22:29, 20 December 2024
  • avoid the use of extended precision on x86 machines with the traditional x87 floating-point architecture. Although it was easy to control calculation...
    6 KB (668 words) - 00:12, 17 October 2024
  • to bring extra precision in intermediate computations for platforms like x87. Thus a modifier strictfp was introduced to enforce strict IEEE 754 computations...
    20 KB (1,887 words) - 11:09, 12 November 2024
  • Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while the privileged...
    38 KB (1,706 words) - 11:38, 15 October 2024
  • the MMX instruction set. MMX had two main problems: it re-used existing x87 floating-point registers making the CPUs unable to work on both floating-point...
    13 KB (1,523 words) - 20:30, 8 October 2024
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    the 80486; it also allows faster access and storage of 64-bit and 80-bit x87 FPU data. Separation of code and data caches lessens the fetch and operand...
    37 KB (3,593 words) - 06:37, 24 November 2024
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    expressions (see IEEE 754 design rationale) and is the designed default method for x87 hardware, but yields unintuitive behavior for the unwary user; FLT_EVAL_METHOD...
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  • extended precision binary number must have an 'emax' of at least 16383. The x87 80-bit extended format meets this requirement. The original IEEE 754-1985...
    63 KB (7,516 words) - 07:56, 2 November 2024
  • all general purpose registers worked directly with the decoder, and the x87 push stack was located within the floating-point unit itself. Starting with...
    27 KB (4,271 words) - 16:55, 14 December 2024
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    and the 80387 works with the 80386. The combination of an x86 CPU and an x87 coprocessor forms a single multi-chip microprocessor; the two chips are programmed...
    83 KB (9,789 words) - 05:07, 17 December 2024
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    mathematics functions (for example, trigonometric functions) like the Intel x87 family, and required specific software libraries to support their functions...
    15 KB (1,937 words) - 16:23, 28 November 2024
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    the CISC HP 3000 machines and the CISC machines from Tandem Computers. The x87 floating point architecture is an example of a set of registers organised...
    39 KB (4,632 words) - 12:02, 6 September 2024
  • Kahan, a primary designer of the x87 arithmetic and initial IEEE 754 standard proposal notes on the development of the x87 floating point: "An extended format...
    35 KB (4,056 words) - 14:57, 20 December 2024
  • architecture FP64 FP32 FP16 Intel CPU Intel 80486 x87 (32-bit) ? 0.128 ? Intel P5 Pentium Intel P6 Pentium Pro x87 (32-bit) ? 0.5 ? Intel P5 Pentium MMX Intel...
    58 KB (3,376 words) - 14:13, 6 December 2024
  • signal processing applications" (PDF). Casey, Shawn (16 October 2008). "x87 and SSE Floating Point Assists in IA-32: Flush-To-Zero (FTZ) and Denormals-Are-Zero...
    17 KB (1,897 words) - 05:28, 16 December 2024
  • Paulista X74 Campo dos Amarais Observatory SP Observatorio Campo dos Amarais X87 Dogsheaven Observatory DF Dogsheaven Observatory, Brasília X88 Adhara Observatory...
    428 KB (109 words) - 18:45, 16 December 2024
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    the 386DX. The first Cyrix product for the personal computer market was a x87 compatible FPU coprocessor. The Cyrix FasMath 83D87 and 83S87 were introduced...
    30 KB (3,836 words) - 22:55, 21 December 2024
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    486SX, it had no on-board x87 math coprocessor, but unlike the 486SX, it could make use of an Intel i287, 387SX or compatible x87 coprocessor. Due to the...
    13 KB (1,111 words) - 04:13, 10 August 2024
  • values are put in the ST0 x87 register. Registers EAX, ECX, and EDX are caller-saved, and the rest are callee-saved. The x87 floating point registers ST0...
    42 KB (4,712 words) - 12:37, 28 October 2024
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    analysis, most of the code used in PhysX applications at the time was based on x87 instructions without any multithreading optimization. This could cause significant...
    25 KB (2,088 words) - 19:53, 9 October 2024
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    supported) Supports i586 instruction set, without x87. Supports i586 instruction set, without x87. Intel Quark SoC X1000 contains a bug (#71538) that...
    15 KB (1,032 words) - 18:32, 26 June 2024