SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set...
6 KB (673 words) - 22:08, 7 June 2024
support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation) Steppings: A1 All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD...
150 KB (4,443 words) - 21:10, 23 June 2024
SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet Athlon 64 X2 dual-core with one core disabled All models support: MMX, SSE, SSE2, SSE3, Enhanced...
40 KB (674 words) - 12:46, 30 May 2024
on the 64-bit Core microarchitecture. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an...
101 KB (3,933 words) - 09:51, 14 April 2024
SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow! MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V MMX, SSE, SSE2, SSE3, Enhanced...
89 KB (3,396 words) - 21:59, 8 May 2024
up to eight-processor configurations All models support: MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64 All models support up to Unbuffered PC3200...
89 KB (2,189 words) - 20:37, 15 April 2024
core chips or 25 W for dual core chips. All models support: MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet, AMD-V Memory support:...
40 KB (1,103 words) - 21:26, 12 July 2023
post-Diamondville Atom microprocessors. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Hyper-Threading Transistors:...
86 KB (3,164 words) - 15:09, 23 April 2024
dual-core, 1 MB on tri- and quad-core models MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, Cool'n'Quiet, AMD-V GPU: TeraScale 2 (Evergreen);...
186 KB (10,618 words) - 05:39, 24 May 2024
Core 5 and Core 7 branded processors. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an...
469 KB (13,605 words) - 00:55, 30 June 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)...
36 KB (331 words) - 04:57, 29 January 2024
that work on MMX registers. SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3 and SSE4. Because it supports floating-point math, it had wider applications...
13 KB (1,523 words) - 12:15, 28 April 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, F16C, BMI1 (Bit Manipulation Instructions1), BMI2, Enhanced Intel SpeedStep...
37 KB (445 words) - 04:02, 16 April 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX2, AVX-512, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an...
46 KB (648 words) - 12:09, 28 April 2024
from Conroe with half L2 cache disabled All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Intel VT-x All models...
44 KB (877 words) - 22:09, 8 May 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)...
25 KB (336 words) - 20:09, 15 April 2024
processors. All models support: MMX, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Advanced Vector Extensions (AVX), Enhanced Intel...
34 KB (431 words) - 14:15, 16 April 2024
SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit AMD64 supported by: all models with an OPN ending in BW All models support: MMX, SSE, SSE2, SSE3, Enhanced 3DNow...
28 KB (861 words) - 05:21, 2 March 2023
X3430 support Hyper-Threading All models support: MMX, XD bit, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Intel 64, SpeedStep, Turbo Boost, Smart Cache, VT-x...
39 KB (763 words) - 12:24, 30 January 2024
CPU/GPU operation when the thermal specification permits MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3,...
28 KB (1,744 words) - 10:15, 4 March 2024
+ Instructions) L2-Cache: 128/256 KiB, full speed MMX, 3DNow!, SSE, SSE2 SSE3 support on E3 and E6 steppings AMD64 on E6 stepping Cool'n'Quiet (Sempron...
17 KB (1,362 words) - 02:40, 25 February 2024
with two cores and L3 cache disabled All models support: MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet, AMD-V, Turbo Core...
31 KB (1,445 words) - 18:44, 15 August 2023
SSE3, SSE4a, ABM, NX bit, AMD64, Cool'n'Quiet, AMD-V Models: Sempron 130-150 Two AMD K10 cores ISA extensions: MMX, Enhanced 3DNow!, SSE, SSE2, SSE3,...
78 KB (5,570 words) - 04:24, 28 June 2024
models support: MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow! All models support: MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64...
19 KB (376 words) - 15:40, 14 October 2023
produced on the 90 nm fabrication process. Both also included support for the SSE3 instruction set, a new feature that had been included in the rival Pentium...
52 KB (5,382 words) - 14:32, 16 November 2023
D0), Intel Family 15 Model 4 (E0, G1) All models support: MMX, SSE, SSE2, SSE3 Intel 64: supported by 5x6, 511 and 519K XD bit (an NX bit implementation):...
52 KB (1,161 words) - 23:19, 11 July 2024
these processors unless noted otherwise. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST),...
19 KB (580 words) - 02:56, 7 February 2023
instruction) L2 cache: 1024 kb (full speed) Instruction sets: MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet FX-55 (2.6 GHz) and FX-57 (2...
19 KB (973 words) - 20:48, 18 May 2024
Athlon 64 ranges of AMD64 64-bit CPUs in 2003. SSE2 was extended to create SSE3 in 2004, and extended once again to create SSE4 in 2006. Most of the SSE2...
9 KB (1,236 words) - 07:35, 28 April 2024
Pentium Extreme Edition 840, 955, and 965. All models support: MMX, SSE, SSE2, SSE3, Intel 64, XD bit (an NX bit implementation) Enhanced Intel SpeedStep Technology...
9 KB (276 words) - 04:04, 16 April 2024