• In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU Identification)...
    218 KB (12,125 words) - 14:57, 7 November 2024
  • CPU-World, CPUID for Intel Xeon 3.40 GHz – Nocona stepping D CPUID without CMPXCHG16B CPU-World, CPUID for Intel Xeon 3.60 GHz – Nocona stepping E CPUID with...
    253 KB (14,070 words) - 22:08, 5 November 2024
  • the Family 0Fh processors. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0F(h) (where the h...
    11 KB (1,142 words) - 10:29, 17 August 2024
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    revision and RAM clock rate. It also provides information on the system's GPU. CPUID Benchmark (computing) GPU-Z Speccy CNET Editors' review (December 2009)...
    2 KB (109 words) - 20:39, 20 September 2024
  • as CPUID family 6 model 22. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model...
    57 KB (3,505 words) - 11:51, 2 September 2024
  • shrink of Intel's Core microarchitecture. Support is indicated via the CPUID.01H:ECX.SSE41[Bit 19] flag. SSE4.2 added STTNI (String and Text New Instructions)...
    23 KB (1,630 words) - 19:50, 3 November 2024
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    P-cores and E-cores on early versions of Alder Lake CPUs reported different CPUID models. This has caused issues with digital rights management systems that...
    56 KB (2,740 words) - 20:53, 30 October 2024
  • instruction rdseed are available with Intel Broadwell CPUs and AMD Zen CPUs. The CPUID instruction can be used on both AMD and Intel CPUs to check whether the...
    24 KB (2,594 words) - 04:47, 31 July 2024
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    by setting the motherboard clock multiplier to 2. Package number: 26050 CPUID: Family 5, Model 8, Stepping 0 L1-Cache: 32 + 32 KiB (Data + Instructions)...
    8 KB (875 words) - 05:26, 5 September 2024
  • processor is earlier than the 486. Starting with the Intel Pentium, the CPUID instruction reports the processor model. However, the above method remains...
    9 KB (805 words) - 10:31, 11 March 2024
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    Physical Address Extension (PAE) but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions)...
    16 KB (1,743 words) - 15:11, 21 October 2024
  • instruction set consists of several separate sets each having their own unique CPUID feature bit. However, they are typically grouped by the processor generation...
    87 KB (4,713 words) - 05:57, 9 October 2024
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    four cores report the same CPUID model 0206A7h and are closely related. The stepping number cannot be seen from the CPUID but only from the PCI configuration...
    58 KB (2,686 words) - 20:41, 19 August 2024
  • are supported modes when the processor is not in long mode. A bit in the CPUID extended attributes field informs programs in real or protected modes if...
    6 KB (713 words) - 10:23, 29 August 2024
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    otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model...
    115 KB (7,794 words) - 15:15, 21 October 2024
  • processor microarchitecture. This is a separate extension using its own CPUID flag and is described on its own page and not below. Intel Haswell processors...
    55 KB (4,507 words) - 15:54, 1 November 2024
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    documentation from Intel, "although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core." The 0.25 μm Tonga core was...
    23 KB (2,472 words) - 15:09, 21 October 2024
  • documentation from Intel, "although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core." The major customer for these...
    12 KB (1,475 words) - 18:50, 29 October 2024
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    the chip identified itself as an 80486 and disabled the CPUID instruction by default. CPUID support could be enabled by first enabling extended CCR registers...
    39 KB (3,181 words) - 21:22, 28 July 2024
  • enabled by the BMI bit in CPUID. Intel officially considers LZCNT as part of BMI, but advertises LZCNT support using the ABM CPUID feature flag. BMI1 is available...
    18 KB (1,412 words) - 23:00, 22 June 2024
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    Photo of CPUID for Transmeta Crusoe TM5800 800 MHz on Fujitsu P2040...
    16 KB (1,683 words) - 20:44, 27 October 2024
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    ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions)...
    15 KB (1,545 words) - 16:48, 9 June 2024
  • operations, and program control, as well as special instructions (e.g., CPUID). In addition to the opcode, many instructions also specify the data (known...
    12 KB (946 words) - 06:37, 28 October 2024
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    a smaller L2 cache. Merom-L has only one processor core and a different CPUID model. The desktop version of Merom is Conroe and the dual-socket server...
    12 KB (993 words) - 12:12, 16 December 2023
  • die and memory controller die resulted in increased memory latency. The CPUID for Clarkdale is family 6, model 37 (2065x). The mobile equivalent of Clarkdale...
    6 KB (420 words) - 01:30, 12 December 2023
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    microarchitecture, the shrink of the Merom microarchitecture to 45 nanometers as CPUID model 23. This replaced the Conroe processor with Wolfdale. The Wolfdale...
    7 KB (516 words) - 02:19, 16 April 2024
  • the Skylake microarchitecture. Support for SGX in the CPU is indicated in CPUID "Structured Extended feature Leaf", EBX bit 02, but its availability to...
    21 KB (2,129 words) - 15:59, 15 October 2024
  • memory and bus interface. The product code for Lynnfield is 80605, its CPUID value identifies it as family 6, model 30 (0106Ex). Lynnfield is related...
    5 KB (240 words) - 09:10, 28 December 2023
  • tests) despite not being officially supported and not even reported by CPUID. This has also been confirmed by Agner Fog. But other tests gave wrong results...
    19 KB (1,392 words) - 06:43, 28 March 2024
  • can solve this problem by inserting a serializing instruction, such as CPUID, to force every preceding instruction to complete before allowing the program...
    10 KB (1,156 words) - 10:41, 16 September 2024