SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September...
23 KB (1,630 words) - 00:49, 16 August 2024
Both have cores. Requires firmware support. Requires firmware support. No SSE4. No SSSE3. Single-precision performance is calculated from the base (or boost)...
198 KB (11,377 words) - 06:35, 22 August 2024
nm "Ironlake" GPU. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX...
150 KB (4,443 words) - 21:10, 23 June 2024
Intel Upgrade Service. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX...
101 KB (3,933 words) - 09:25, 25 July 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX2, AVX-512, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an...
46 KB (648 words) - 12:09, 28 April 2024
(7.34 mm x 8.89 mm) All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX...
86 KB (3,164 words) - 09:36, 25 July 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, F16C, BMI1 (Bit Manipulation Instructions1), BMI2, Enhanced Intel SpeedStep...
37 KB (445 words) - 04:02, 16 April 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)...
25 KB (336 words) - 20:09, 15 April 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)...
36 KB (331 words) - 04:57, 29 January 2024
PC3-10600 DDR3 SDRAM All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, IOMMU, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, CVT16–F16C, XOP...
87 KB (2,169 words) - 19:03, 26 September 2024
Penryn microarchitecture All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit...
44 KB (877 words) - 10:18, 25 July 2024
models support: MMX, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Advanced Vector Extensions (AVX), Enhanced Intel SpeedStep Technology...
34 KB (431 words) - 22:11, 10 August 2024
processors (Sandy Bridge) available at its introduction (including SSSE3, SSE4.1, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD;...
36 KB (3,748 words) - 19:04, 19 September 2024
registers. SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3 and SSE4. Because it supports floating-point math, it had wider applications than...
13 KB (1,523 words) - 12:15, 28 April 2024
Intel X99 chipset. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit...
65 KB (2,033 words) - 16:46, 6 July 2024
the thermal specification permits MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM...
28 KB (1,744 words) - 10:15, 4 March 2024
Hyper-Threading All models support: MMX, XD bit, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Intel 64, SpeedStep, Turbo Boost, Smart Cache, VT-x, EPT, VT-d, TXT...
39 KB (763 words) - 12:24, 30 January 2024
since the release of Windows 11, as follows: A x86-64-v2 CPU supporting SSE4.2 and POPCNT CPU instructions is now required, otherwise the Windows kernel...
41 KB (1,283 words) - 00:38, 25 September 2024
×143 mm2 Steppings: B3, G0 All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit...
474 KB (13,712 words) - 21:47, 8 September 2024
instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction),...
23 KB (1,049 words) - 22:43, 6 September 2024
unless noted otherwise. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit...
19 KB (580 words) - 02:56, 7 February 2023
architecture 3D tri-gate transistors Consumer chips up to four cores Supports SSE4.2 instruction set Supports Intel AESNI and PCLMUL instructions Supports Intel...
11 KB (507 words) - 04:06, 16 April 2024
separate L3 cache. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD...
19 KB (1,203 words) - 08:44, 14 April 2024
since the release of Windows 11, as follows: A x86-64-v2 CPU supporting SSE4.2 and POPCNT CPU instructions is now required, otherwise the Windows kernel...
7 KB (3,086 words) - 03:32, 16 September 2024
sockets 2 dies per socket All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, FMA3, MPX, Enhanced Intel SpeedStep Technology...
40 KB (212 words) - 07:23, 4 March 2024
found in an 8-core configuration. Penryn added support for a subset for SSE4 (SSE4.1). Bloomfield and Gainestown introduced a number of notable features...
70 KB (1,893 words) - 08:03, 23 August 2024
bug.[citation needed] All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit...
106 KB (4,981 words) - 22:46, 6 September 2024
SSE2 was extended to create SSE3 in 2004, and extended once again to create SSE4 in 2006. Most of the SSE2 instructions implement the integer vector operations...
9 KB (1,236 words) - 08:21, 14 August 2024
x86-64 Extensions AES-NI CLMUL RDRAND SHA TXT MMX SSE SSE2 SSE3 SSSE3 SSE4 SSE4.1 SSE4.2 AVX AVX2 AVX-512 AVX-VNNI AVX-IFMA FMA3 TSX AMX P-core architecture...
24 KB (1,952 words) - 13:25, 26 September 2024
Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX, VT-x, VT-d Products, models...
18 KB (1,440 words) - 23:39, 6 August 2024