Domino logic

For logic gates built from dominoes, see Domino computer.
General domino logic implementation, with the pull-down network symbolising a network of NMOS transistors.[1]

Domino logic is a CMOS-based evolution of dynamic logic techniques consisting of a dynamic logic gate cascaded into a static CMOS inverter.[2] The term derives from the fact that in domino logic, each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Domino logic contrasts with other solutions to the cascade problem where cascading is interrupted by clocks or other means.

Domino logic was developed to speed up circuits, solving the premature cascade problem, typically by inserting static CMOS inverters between domino stages to avoid premature discharge of further cascaded dynamic logic gates.[3] Domino logic allows a rail-to-rail logic swing, with the output being able to switch from the power supply voltage to the ground voltage.

Dynamic logic

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Main article: Dynamic logic (digital electronics)

Dynamic logic differs from static logic by including a clock signal to speed up performance. In CMOS dynamic logic gates, the gate output is precharged to the power supply voltage while the clock is off (the "precharge" phase), and then is evaluated to the correct logic state while the clock is on (the "evaluation" phase) by draining the relevant NMOS transistors in the pull-down network.[2]

When cascading dynamic logic gates, however, a problem arises: the precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the precharge of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.[4]

Domino logic operation

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In order to cascade dynamic logic gates, one solution is domino logic, which inserts an ordinary static inverter between stages. In a multistage domino logic cascade structure, the evaluation of each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Once evaluated, the node states cannot return to "1" until the next precharge phase begins.[3]

While the insertion of the inverter might seem to defeat the point of dynamic logic, since the inverter has a pFET (one of the main goals of dynamic logic is to avoid pFETs where possible, due to speed), there are two reasons it works well. First, there is no fan-out to multiple pFETs; the dynamic gate connects to exactly one inverter, so the gate is still very fast. Furthermore, since the inverter connects to only nFETs in dynamic logic gates, it too is very fast. Second, the pFET in an inverter can be made smaller than in some types of logic gates.[5]

Modifications to domino logic

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Charge sharing can cause difficulties for domino logic signal integrity; during the evaluation phase, NMOS transistors next to the output which are on may cause undesired discharging from the output node. To fix this, a keeper transistor can be used. This keeper transistor is a PMOS transistor with its gate connected to the inverter output, its source connected to the power supply, and its drain connected to the inverter input. The keeper transistor thus connects the dynamic node to the power supply whenever it is supposed to be in the "1" state, allowing the output to be correctly restored despite the charge sharing.[6]

Another issue in domino logic is its noninverting property; that is, it can only implement gates that do not have inversions at their outputs (such as AND gates and OR gates, as opposed to NAND gates and NOR gates). To rectify this property, some variants of domino logic are differential or dual-rail in nature, using inverted as well as non-inverted inputs to implement the logic function as well as its inverse. These varieties also include cross-coupled pFETs to attenuate noise.[2]

Traditional domino logic circuits are "footed", that is, they have an NMOS transistor controlled by the clock which is connected to the ground rail. Some domino logic circuits, however, are "footless": they lack this transistor, resulting in higher speed at the cost of greater power leakage.[7]

See also

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References

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  1. ^ Sharma, Ankita; Rao, Divyanshu; Mohan, Ravi (December 2016). "Design and Implementation of Domino Logic Circuit in CMOS" (PDF). Journal of Network Communications and Emerging Technologies. 6 (12): 14–17.
  2. ^ a b c Srivastava, P.; Pua, A.; Welch, L. (1998). "Issues in the design of domino logic circuits". Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222). IEEE Comput. Soc. pp. 108–112. doi:10.1109/GLSV.1998.665208. ISBN 978-0-8186-8409-8. S2CID 45670900.
  3. ^ a b Natarajan, Suriyaprakash; Gupta, Sandeep K.; Breuer, Melvin A. (2001). Proceedings International Test Conference 2001 (Cat. No.01CH37260). Vol. 13. IEEE. pp. 367–376. doi:10.1109/test.2001.966628. ISBN 0-7803-7169-0.
  4. ^ Knepper, R.W. "5. Dynamic Logic Circuits". SC571 VLSI Design Principles. Boston University.
  5. ^ WO 2000/076068, Abdel-Hafeez, S. & Ranjan, N., "Single Rail Domino Logic For Four-Phase Clocking Scheme", published 2000 
  6. ^ Garg, Sandeep; Gupta, Tarun Kumar (2018-08-01). "Low power domino logic circuits in deep-submicron technology using CMOS". Engineering Science and Technology. 21 (4): 625–638. doi:10.1016/j.jestch.2018.06.013. ISSN 2215-0986.
  7. ^ Angeline, A. Anita; Bhaaskaran, V. S. Kanchana (2022-04-01). "Domino Logic Keeper Circuit Design Techniques: A Review". Journal of the Institution of Engineers (India): Series B. 103 (2): 669–679. doi:10.1007/s40031-021-00668-5. ISSN 2250-2114. S2CID 256342548.

General references

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