Hazard (logic)

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In digital logic, a hazard is an undesirable effect caused by either a deficiency in the system or external influences in both synchronous^{[citation needed]} and asynchronous circuits.^[1]: 43 Logic hazards are manifestations of a problem in which changes in the input variables do not change the output correctly due to some form of delay caused by logic elements (NOT, AND, OR gates, etc.) This results in the logic not performing its function properly. The three different most common kinds of hazards are usually referred to as static, dynamic and function hazards.

Hazards are a temporary problem, as the logic circuit will eventually settle to the desired function. Therefore, in synchronous designs, it is standard practice to register the output of a circuit before it is being used in a different clock domain or routed out of the system, so that hazards do not cause any problems. If that is not the case, however, it is imperative that hazards be eliminated as they can have an effect on other connected systems.

A static hazard is a change of a signal state twice in a row when the signal is expected to stay constant.^[1]: 48 When one input signal changes, the output changes momentarily before stabilizing to the correct value. There are two types of static hazards:

• Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily changes to 0,1 before settling on 1
• Static-0 Hazard: the output is currently 0 and after the inputs change, the output momentarily changes to 1,0 before settling on 0

In properly formed two-level AND-OR logic based on a Sum Of Products expression, there will be no static-0 hazards (but may still have static-1 hazards). Conversely, there will be no static-1 hazards in an OR-AND implementation of a Product Of Sums expression (but may still have static-0 hazards).

The most commonly used method to eliminate static hazards is to add redundant logic (consensus terms in the logic expression).

Consider an imperfect circuit that suffers from a delay in the physical logic elements i.e. AND gates etc.

The simple circuit performs the function noting:

${\displaystyle {\overline {f(A,B,C)}}=AB+{\overline {A}}C}$

From a look at the starting diagram it is clear that if no delays were to occur, then the circuit would function normally. However, no two gates are ever manufactured exactly the same. Due to this imperfection, the delay for the first AND gate will be slightly different than its counterpart. Thus an error occurs when the input changes e and the solution on how to solve this problem, we would look to the Karnaugh map. The two gates are shown by solid rings, and the hazard can be seen under the dashed ring. A theorem proved by Huffman^[2] tells us that by adding a redundant loop 'BC' this will eliminate the hazard.

So our original function is now:

${\displaystyle {\overline {f(A,B,C)}}=AB+{\overline {A}}C+BC}$

Now we can see that even with imperfect logic elements, our example will not show signs of hazards when A changes state. This theory can be applied to any logic system. Computer programs deal with most of this work now, but for simple examples it is quicker to do the debugging by hand. When there are many input variables (say 6 or more) it will become quite difficult to 'see' the errors on a Karnaugh map.

A dynamic hazard are a series of changes of a signal state that happen several times in a row when the signal is expected to change state only once.^[1]: 48 A dynamic hazard is the possibility of an output changing more than once as a result of a single input change.

Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input). If each route has a different delay, then it quickly becomes clear that there is the potential for changing output values that differ from the required / expected output.

E.g. A logic circuit is meant to change output state from 1 to 0, but instead changes from 1 to 0 then 1 and finally rests at the correct value 0. This is a dynamic hazard.

As a rule, dynamic hazards are more complex to resolve, but note that if all static hazards have been eliminated from a circuit, then dynamic hazards cannot occur.

In contrast to static and dynamic hazards, functional hazards are ones caused by a change applied to more than one input. There is no specific logical solution to eliminate them. One really reliable method is preventing inputs from changing simultaneously, which is not applicable in some cases. So, circuits should be carefully designed to have equal delays in each path.^[3]

Combinational logic hazards

In combinational logic is a hazard that depend on the distribution of signal propagation delays in the logic circuits and overall design of a logic circuit function implemented.^[1]: 43

Combinational functional hazards

In combinational logic are hazards that can be detected and suppressed at a higher level of programming, by studying and modifying the output logic function.^[1]: 43

Sequential hazards

Is a kind of undesirable signal changes found in looped systems.^[1]: 43

• Don't care
• Glitch
• Hazard (computer architecture)
• Race condition

• Floating body effect, a probably cause for hazard silicon on Insulator-devices

• http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/02-Hazards/hazards.htm#FunctionHazards