French
DeutschLatticeMico8
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| Designer | Lattice Semiconductor |
|---|---|
| Bits | 8-bit |
| Design | RISC |
| Open | No |
| Registers | |
| General-purpose | 32 |
The LatticeMico8 is an 8-bit microcontroller reduced instruction set computer (RISC) soft processor core optimized for field-programmable gate arrays (FPGAs) and crossover programmable logic device architecture from Lattice Semiconductor. Combining a full 18-bit wide instruction set with 32 general purpose registers, the LatticeMico8 is a flexible Verilog reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 lookup tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
The LatticeMico8 is licensed under a new free (IP) core license, the first such license offered by any FPGA supplier. The main benefits of using the IP core are greater flexibility, improved portability, and no cost. This new agreement provides some of the benefits of standard open-source licenses and allows users to mix proprietary designs with the core. Further, it allows for distributing designs in bitstream or FPGA format without accompanying it with a copy of the license. Developers are required to keep the core's source code confidential and use "for the sole purposes of design documentation and preparation of Derivative Works ... to develop designs to program Lattice programmable logic devices".[1]
Features
[edit]- 8-bit data path
- 18-bit wide instructions
- 32 general purpose registers
- 32 bytes of internal scratch pad memory
- Input/output is performed using "Ports" (up to 256 port numbers)
- Optional 256 bytes of external scratch pad RAM
- Two cycles per instruction
- Lattice UART reference design peripheral
References
[edit]- ^ "Reference Design with Source Code License Agreement". Retrieved 2011-02-01.
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