Nord-5

Nord-5 was Norsk Data's first 32-bit minicomputer and was claimed to be the first 32-bit minicomputer,^[1] subject to various qualifications, being described in company literature as "a general purpose 32 bit high speed compute module designed to be attached to a general purpose NORD computer system".^[2] Such qualifications were more clearly noted for its successor, the Nord-50, itself being described as a "special purpose computer" and having a similar reliance on a Nord-10 host computer.^[3]: I-I-I

Introduced in 1972, the Nord-5 was categorised as a "superminicomputer", described retrospectively as a "technological success but a commercial disaster", eventually being superseded in 1983 by the ND-500 family.^[4] Initially described as a larger version of the Nord-1 to compete with the UNIVAC 1106 and the IBM System/360 Model 44,^[5] the machine used a Nord-1 as its front-end console processor, which ran the majority of the OS.^[2]

The Nord-50 provided a CPU that does not support dedicated input/output instructions, interrupt-related instructions or memory management functions, these being delegated to the Nord-10 host computer.^[3]: I-I-I The machine's CPU provides three classes of instructions, each supporting a range of data manipulation operations, divided into those performing memory accesses, those operating on internal or external registers, and those combining register values with a constant operand or argument.^[6]

The implementation of the Nord-50's CPU used TTL integrated circuits, employing SN7489 64-bit RAM chips for register storage,^{[3]: III-5-1} and the SN74181 arithmetic logic unit. The latter influenced the instruction encoding supported by the CPU, with the 74181's function select input encoding influencing the memory addressing instruction's function code field.^{[3]: III-6-1}

The CPU provides 64 general registers, 32 bits in size, denoted GR₀ through to GR₆₃. Floating-point arithmetic being a core feature of the system, floating-point operations also use these registers, with single-precision floating registers FR₀ through FR₁₅ corresponding to GR₀ through GR₁₅ and FR₃₂ through FR₄₇ corresponding to GR₃₂ through GR₄₇. The discontinuity in floating register provision is explained by the treatment of double-precision values, these involving double-precision floating registers that employ pairs of general registers. Thus, FDR₀ through FDR₁₅ each employ a register from GR₀ through GR₁₅ for the most significant word of the 64-bit representation, pairing that register with one from GR₁₆ through GR₃₁ for the least significant word. Similarly, FDR₃₂ through FDR₄₇ pairs registers from GR₃₂ through GR₄₇ with those from GR₄₈ through GR₆₃.^[6]

The first sixteen general registers are more versatile in that they may be used in the base register or index register role in memory access instructions, thus providing base registers BR₀ through BR₁₅ and index registers IR₀ through IR₁₅. The second sixteen general registers also assume a special role as modification registers under certain circumstances, with MR₀ through MR₁₅ corresponding to GR₁₆ through GR₃₁.^[6]

Special registers dedicated to particular roles include an overflow register (OR) applicable to multiplication and a remainder register (RR) applicable to division. The program counter register (P) holds the address of the instruction being read from memory, and the instruction register (IR) contains the currently executed instruction.^[6]

Memory reference instructions involve the computation of an effective memory address and access to this computed location. Such instructions can involve direct or indirect addressing. Direct addressing involves the computation of the effective address from the instruction operands provided in the instruction word:

With the I field set to zero, the effective address is computed using the indicated base and index registers, adding the displacement value (Ea = R_B + R_X + D), with this address then employed by the function indicated by the FC field. The register designator field indicates a register also employed by the indicated function. Functions provided include transfers between registers and memory, arithmetic operations whose results are placed in registers, and conditional jump operations testing register values and jumping to the effective address. Familiar operations such as a return jump, storing the return address in a register, are also among the functions provided. More unusual operations include conditional skip operations comparing register values with values retrieved from the effective address, potentially causing the next instruction in the stream to be skipped. Remote execution involves the execution of an instruction retrieved from the effective address or even the execution of the computed address value itself, interpreted as an instruction.^[6]

Indirect addressing ostensibly builds on the remote execution mechanism to compute an effective address, utilising a simpler form of the memory reference instruction, incorporating a potentially greater displacement value but omitting a function:

The 32-bit word at the computed effective address location is then obtained to provide the details of a new effective address, this word having the form of a memory reference instruction itself. Thus, an instruction is effectively loaded from outside the regular instruction stream and executed. Where an indirect reference is obtained, the cycle of obtaining a new effective address repeats, and the chaining of up to 16 indirect references is permitted by the architecture, terminated by a direct reference.^[6]