Verilator

Verilator^[1]

Developer(s)	Wilson Snyder
Repository	github.com/verilator/verilator
Written in	C++
Operating system	Linux, FreeBSD, Microsoft Windows (via Cygwin[2])
Type	Simulator
License	LGPL-3.0-only or Artistic-2.0
Website	verilator.org

Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free electronic design automation (EDA) software.

Verilator has seen its widest adoption in the academic and open-source communities. The semiconductor industry has been more cautious in its adoption of an open-source tool, and has the financial means to use commercial alternatives.^[3]

Researchers have used Verilator to develop new co-simulation environments,^[4] as part of general ASIC and FPGA design flows^[5][6] and in performance and power analysis.^[7] Verilator is also a popular tool for student dissertations, for example.^[8]

Verilator is an open-source tool, and has in turn been adopted by a number of other projects. The Fedora Electronic Lab has adopted Verilator as part of its open source design flow for Fedora 11. The OpenRISC architecture from OpenCores includes a cycle accurate reference model, generated from Verilog using Verilator. A 2010 paper described how the regression test suite for GCC could be run against a Verilator model of the OpenRISC 1200 as a way of detecting errors in the Verilog RTL implementation.^[9] TestDrive Profiling Master tool provides the virtual FPGA environment using Verilator.

Commercially, Philips Semiconductors (now NXP) have led the way.^[10] Their use of Verilator is becoming more widespread, for example within application notes.^[11] More recently Art of Silicon have described their use of Verilator on a farm of Linux processors as a route to faster regression testing of their commercial designs.^[12][13] The current maintainer of Verilator identified^[14] 27 companies and universities who had reported use of Verilator or contributed to its development, including Intel, Arm, CSR, Broadcom, Raytheon, Infineon, Stanford University, Imperial College London and Embecosm.

Verilator's user manual provides a short history.^[15] The tool originated in 1994 with a team led by Paul Wasson at the Core Logic Group at Digital Equipment Corporation (DEC). It was used to convert Verilog code to C for co-simulation with a C based CPU model of the Alpha processor. During the mid-1990s Duane Galbi took over responsibility for development and the technology was adopted by other groups in DEC. In 1998 DEC released the source code.

Since 2001 the technology has been developed by Wilson Snyder and others as part of the Veripool open source project. A SystemC mode was added and the tool rewritten from scratch in C++, leading to an increase in performance. In 2022 Verilator Version 5 added an IEEE-compliant scheduler and delay semantics, relaxing previous restrictions that ignored all delays.

Verilator converts Verilog to C++ or SystemC. It can handle all versions of Verilog and also some SystemVerilog assertions. The approach is closer to synthesis than event-driven simulation. The entire design is flattened (that is, all modules are expanded to create one module). Static analysis is used to eliminate wires and schedule all processes at model generation time. A C++ class is generated with a function which takes 2-state values on input ports and advance them to values on output ports at the next clock edge.

SystemC is supported by providing a wrapper class using SystemC ports and with sensitivity to the clock(s), which will drive the ports of the underlying C++ model.

Verilator supports automatically partitioning designs into multiple threads, also potentially improving performance.

This section needs expansion. You can help by adding to it. (March 2009)

Verilator converts synthesizable Verilog to C++, while C++ library could be compiled into a MEX file using MATLAB interface to C++. This is how Verilog designs can be directly simulated from MATLAB. Using compiled C++ models with MATLAB is faster than using co-simulation interfaces with a separate HDL simulator. There is an open-source project called vmodel that compiles Verilog into a MEX file using Verilator and provides a set of functions for model simulation from MATLAB.

• Comparison of EDA software
• List of HDL simulators
• OpenCores
• OpenRISC
• Verilog

• Official website
• vmodel – Github